87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
// Copyright 2009-2020 Intel Corporation
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// SPDX-License-Identifier: Apache-2.0
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#pragma once
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/* Make precision match SSE, at the cost of some performance */
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#if !defined(__aarch64__)
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# define SSE2NEON_PRECISE_DIV 1
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# define SSE2NEON_PRECISE_SQRT 1
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#endif
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#include "sse2neon.h"
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__forceinline __m128 _mm_abs_ps(__m128 a) { return vabsq_f32(a); }
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__forceinline __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c) { return vfmaq_f32(c, a, b); }
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__forceinline __m128 _mm_fnmadd_ps(__m128 a, __m128 b, __m128 c) { return vfmsq_f32(c, a, b); }
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__forceinline __m128 _mm_fnmsub_ps(__m128 a, __m128 b, __m128 c) { return vnegq_f32(vfmaq_f32(c, a, b)); }
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__forceinline __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c) { return vnegq_f32(vfmsq_f32(c, a, b)); }
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__forceinline __m128 _mm_broadcast_ss (float const * mem_addr)
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{
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return vdupq_n_f32(*mem_addr);
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}
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// AVX2 emulation leverages Intel FMA defs above. Include after them.
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#include "avx2neon.h"
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/* Dummy defines for floating point control */
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#define _MM_MASK_MASK 0x1f80
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#define _MM_MASK_DIV_ZERO 0x200
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// #define _MM_FLUSH_ZERO_ON 0x8000
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#define _MM_MASK_DENORM 0x100
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#define _MM_SET_EXCEPTION_MASK(x)
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// #define _MM_SET_FLUSH_ZERO_MODE(x)
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/*
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__forceinline int _mm_getcsr()
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{
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return 0;
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}
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__forceinline void _mm_mfence()
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{
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__sync_synchronize();
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}
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*/
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__forceinline __m128i _mm_load4epu8_epi32(__m128i *ptr)
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{
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uint8x8_t t0 = vld1_u8((uint8_t*)ptr);
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uint16x8_t t1 = vmovl_u8(t0);
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uint32x4_t t2 = vmovl_u16(vget_low_u16(t1));
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return vreinterpretq_s32_u32(t2);
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}
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__forceinline __m128i _mm_load4epu16_epi32(__m128i *ptr)
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{
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uint16x8_t t0 = vld1q_u16((uint16_t*)ptr);
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uint32x4_t t1 = vmovl_u16(vget_low_u16(t0));
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return vreinterpretq_s32_u32(t1);
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}
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__forceinline __m128i _mm_load4epi8_f32(__m128i *ptr)
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{
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int8x8_t t0 = vld1_s8((int8_t*)ptr);
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int16x8_t t1 = vmovl_s8(t0);
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int32x4_t t2 = vmovl_s16(vget_low_s16(t1));
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float32x4_t t3 = vcvtq_f32_s32(t2);
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return vreinterpretq_s32_f32(t3);
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}
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__forceinline __m128i _mm_load4epu8_f32(__m128i *ptr)
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{
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uint8x8_t t0 = vld1_u8((uint8_t*)ptr);
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uint16x8_t t1 = vmovl_u8(t0);
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uint32x4_t t2 = vmovl_u16(vget_low_u16(t1));
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return vreinterpretq_s32_u32(t2);
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}
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__forceinline __m128i _mm_load4epi16_f32(__m128i *ptr)
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{
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int16x8_t t0 = vld1q_s16((int16_t*)ptr);
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int32x4_t t1 = vmovl_s16(vget_low_s16(t0));
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float32x4_t t2 = vcvtq_f32_s32(t1);
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return vreinterpretq_s32_f32(t2);
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}
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